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INTEGRATED CIRCUITS
DATA SHEET
PCD3755A; PCD3755E; PCD3755F 8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
Product specification Supersedes data of 1996 Dec 18 File under Integrated Circuits, IC03 1997 Apr 16
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
CONTENTS 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 7 7.1 7.2 7.3 7.4 7.5 7.6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 22.1 22.2 22.3 22.4 23 24 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FREQUENCY GENERATOR Frequency generator derivative registers Melody output (P1.7/MDY) Frequency registers DTMF frequencies Modem frequencies Musical scale frequencies EEPROM AND TIMER 2 ORGANIZATION EEPROM registers EEPROM latches EEPROM flags EEPROM macros EEPROM access Timer 2 DERIVATIVE INTERRUPTS TIMING RESET IDLE MODE STOP MODE INSTRUCTION SET RESTRICTIONS OVERVIEW OF PORT AND POWER-ON-RESET CONFIGURATION OTP PROGRAMMING SUMMARY OF DERIVATIVE REGISTERS HANDLING LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS PACKAGE OUTLINES SOLDERING Reflow soldering Wave soldering DIP Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS 2
PCD3755A; PCD3755E; PCD3755F
1997 Apr 16
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
1 FEATURES 2
PCD3755A; PCD3755E; PCD3755F
GENERAL DESCRIPTION
* 8-bit CPU, ROM, RAM, EEPROM and I/O; in a single 28-lead or 32-lead package * 8 kbytes user-programmable ROM (One-Time Programmable) * 128 bytes RAM * 128 bytes Electrically Erasable Programmable Read-Only Memory (EEPROM) * Over 100 instructions (based on MAB8048) all of 1 or 2 cycles * 20 quasi-bidirectional I/O port lines * 8-bit programmable Timer/event counter 1 * 8-bit reloadable Timer 2 * Three single-level vectored interrupts: - external - 8-bit programmable Timer/event counter 1 - derivative; triggered by reloadable Timer 2 * Two test inputs, one of which also serves as the external interrupt input * DTMF, modem, musical tone generator * Reference for supply and temperature-independent tone output * Filtering for low output distortion (CEPT compatible) * Melody output for ringer application * Power-on-reset * Stop and Idle modes * Supply voltage: 1.8 to 6 V (DTMF tone output and EEPROM erase/write from 2.5 V) * Clock frequency: 1 to 16 MHz (3.58 MHz for DTMF suggested) * Operating temperature: -25 to +70 C * Manufactured in silicon gate CMOS process. 3 ORDERING INFORMATION (see note 1)
This data sheet details the specific properties of the PCD3755A, PCD3755E and PCD3755F. The devices differ in their Port and Power-on-reset configurations. References to `PCD3755x' apply to all three types. The devices are members of the PCD33xxA family of microcontrollers. The shared properties of the family are described in the "PCD33xxA family" data sheet, which should be read in conjunction with this publication. The PCD3755A, PCD3755E and PCD3755F are One-Time Programmable (OTP) microcontrollers designed primarily for telephony applications.They include an on-chip generator for dual tone multifrequency (DTMF), modem and musical tones. In addition to dialling, generated frequencies can be made available as square waves (P1.7/MDY) for melody generation, providing ringer operation. The PCD3755A, PCD3755E and PCD3755F also incorporate 128 bytes of EEPROM. The EEPROM can be used for storing telephone numbers, particularly for implementing redial functions. The Power-on-reset circuitry is extra accurate to accommodate parallel telephones and fax equipment. The instruction set is similar to that of the MAB8048 and is a sub-set of that listed in the "PCD33xxA family" data sheet.
PACKAGE TYPE NUMBER NAME PCD3755xP PCD3755xT PCD3755xH Note 1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type number will also specify the required program and the ROM mask options. DIP28 SO28 LQFP32 DESCRIPTION plastic dual in-line package; 28 leads (600 mil) plastic small outline package; 28 leads; body width 7.5 mm plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm VERSION SOT117-1 SOT136-1 SOT358-1
1997 Apr 16
3
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P2.0 to P2.3 4 PORT 2 BUFFER PORT 2 FLIP-FLOP TONE P1.0 to P1.6 P1.7/MDY 7 RESIDENT OTP-ROM 8 kbytes PORT 0 FLIP-FLOP DECODE SINE WAVE GENERATOR INTERNAL CLOCK FREQ. 30 32 HGF REGISTER LGF REGISTER MELODY CONTROL REGISTER 8 8 T1 MEMORY BANK FLIP-FLOPS P0.0 to P0.7 8 PORT 0 BUFFER FILTER PORT 1 FLIP-FLOP PORT 1 BUFFER TIMER/ EVENT COUNTER HIGHER PROGRAM COUNTER LOWER PROGRAM COUNTER PROGRAM STATUS WORD 8 8 8 4 8 8
4
Philips Semiconductors
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
BLOCK DIAGRAM
PCD3755x
8
5
8
8
8 TIMER 2 REGISTER
8 EEPROM CONTROL REGISTER
8 EEPROM ADDRESS REGISTER
8 EEPROM DATA TRANSFER
8 INTERRUPT LOGIC
8
8
8
8
8
8
8 MULTIPLEXER REGISTER 0 REGISTER 1 REGISTER 2 REGISTER 3 REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7 8 LEVEL STACK (VARIABLE LENGTH) OPTIONAL SECOND REGISTER BANK
Fig.1 Block diagram.
handbook, full pagewidth
4
TIMER 2 RELOAD REGISTER ACCUMULATOR TEMPORARY REGISTER 2 TEMPORARY REGISTER 1 RAM ADDRESS REGISTER ARITHMETIC INSTRUCTION REGISTER AND DECODER timer interrupt derivative interrupt EEPROM 128 bytes
POWER-ON-RESET VPOR
LOGIC UNIT external interrupt CONDITIONAL DECIMAL ADJUST STOP IDLE CE/T0 INTERRUPT BRANCH LOGIC CONTROL AND TIMING RESET INITIALIZE XTAL1 XTAL2
T1 CE/T0 TIMER FLAG CARRY ACC ACC BIT TEST
MBG639
D E C O D E
PCD3755A; PCD3755E; PCD3755F
RESET
DATA STORE
RESIDENT RAM ARRAY 128 bytes
OSCILLATOR
Product specification
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
5 5.1 PINNING INFORMATION Pinning
handbook, halfpage
PCD3755A; PCD3755E; PCD3755F
P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 T1 XTAL1
1 2 3 4 5 6 7
28 P0.0 27 P2.3 26 P2.2 25 P2.1 24 VDD 23 TONE 22 V
SS PCD3755xP PCD3755xT 21 P2.0 8 9 20 P1.7/MDY 19 P1.6 18 P1.5 17 P1.4 16 P1.3 15 P1.2
MBG640
XTAL2 10 RESET 11 CE/T0 12 P1.0 13 P1.1 14
Fig.2 Pin configuration (SOT117-1 and SOT136-1).
32 P0.4
31 P0.3
30 P0.2
29 P0.1
27 P0.0
26 P2.3
n.c. P0.5 P0.6 P0.7 T1 XTAL1 XTAL2 RESET
28 n.c.
handbook, full pagewidth
25 P2.2
1 2 3 4
24 P2.1 23 VDD 22 TONE 21 VSS 20 P2.0 19 P1.7/MDY 18 P1.6 17 n.c.
PCD3755xH
5 6 7 8
P1.0 10
P1.1 11
P1.2 12
n.c. 13
P1.3 14
P1.4 15
P1.5 16
9
MBG641
Fig.3 Pin configuration (SOT358-1).
1997 Apr 16
CE/T0
5
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
5.2 Pin description
PCD3755A; PCD3755E; PCD3755F
Table 1
SOT117-1 and SOT136-1 packages (for information on parallel I/O ports, see Chapter 14) PIN 1 to 7 8 9 10 11 12 13 to 19 20 21 22 23 24 25 to 27 28 TYPE I/O I I O I I I/O I/O I/O P O P I/O I/O DESCRIPTION 7 bits of Port 0: 8-bit quasi-bidirectional I/O port Test 1 or count input of 8-bit Timer/event counter 1 crystal oscillator or external clock input crystal oscillator output reset input Chip Enable or Test 0 7 bits of Port 1: 8-bit quasi-bidirectional I/O port 1 bit of Port 1: 8-bit quasi-bidirectional I/O port; or melody output 1 bit of Port 2: 4-bit quasi-bidirectional I/O port ground DTMF output positive supply voltage 3 bits of Port 2: 4-bit quasi-bidirectional I/O port 1 bit of Port 0: 8-bit quasi-bidirectional I/O port
SYMBOL P1.1 to P0.7 T1 XTAL1 XTAL2 RESET CE/T0 P1.0 to P1.6 P1.7/MDY P2.0 VSS TONE VDD P2.1 to P2.3 P0.0 Table 2
SOT358-1 package (for information on parallel I/O ports, see Chapter 14) PIN 1, 13, 17, 28 2 to 4 5 6 7 8 9 10 to 12, 14 to 16, 18 19 20 21 22 23 24 to 26 27, 29 to 32 TYPE - I/O I I O I I I/O I/O I/O P O P I/O I/O not connected 3 bits of Port 0: 8-bit quasi-bidirectional I/O port Test 1 or count input of 8-bit Timer/event counter 1 crystal oscillator or external clock input crystal oscillator output reset input Chip Enable or Test 0 7 bits of Port 1: 8-bit quasi-bidirectional I/O port 1 bit of Port 1: 8-bit quasi-bidirectional I/O port; or melody output 1 bit of Port 2: 4-bit quasi-bidirectional I/O port ground DTMF output positive supply voltage 3 bits of Port 2: 4-bit quasi-bidirectional I/O port 5 bits of Port 0: 8-bit quasi-bidirectional I/O port DESCRIPTION
SYMBOL n.c. P0.5 to P0.7 T1 XTAL1 XTAL2 RESET CE/T0 P1.0 to P1.6 P1.7/MDY P2.0 VSS TONE VDD P2.1 to P2.3 P0.0 to P0.4
1997 Apr 16
6
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
6 FREQUENCY GENERATOR
PCD3755A; PCD3755E; PCD3755F
A versatile frequency generator section is provided (see Fig.4). For normal operation, use a 3.58 MHz quartz crystal or PXE resonator. The frequency generator includes precision circuitry for dual tone multifrequency (DTMF) signals, which is typically used for tone dialling telephone sets. Their frequencies are provided in purely sinusoidal form on the TONE output or as square waves on the P1.7/MDY output. 6.1 6.1.1 Frequency generator derivative registers HIGH AND LOW GROUP FREQUENCY REGISTERS
The TONE output can alternatively issue twelve modem frequencies for data rates between 300 and 1200 bits/s. In addition to DTMF and modem frequencies, two octaves of musical scale in steps of semitones are available. In case no tones are generated the TONE output is in 3-state mode.
Table 3 gives the addresses, mnemonics and access types of the High Group Frequency (HGF) and Low Group Frequency (LGF) registers. Table 3 Hexadecimal addresses, mnemonics, access types and bit mnemonics of the frequency registers REGISTER MNEMONIC HGF LGF ACCESS TYPE W W BIT MNEMONICS 7 H7 L7 6 H6 L6 5 H5 L5 4 H4 L4 3 H3 L3 2 H2 L2 1 H1 L1 0 H0 L0
REGISTER ADDRESS 11H 12H 6.1.2
MELODY CONTROL REGISTER (MDYCON)
MDYCON is a R/W register. Table 4 7 0 Table 5 BIT 7 to 1 0 Melody Control Register (address 13H) 6 0 5 0 4 0 3 0 2 0 1 0 0 EMO
Description of MDYCON bits MNEMONIC - EMO These bits are set to a logic 0. Enable Melody Output. If bit EMO = 0, then P1.7/MDY is a standard port line. If bit EMO = 1, then P1.7/MDY is the melody output. EMO = 1 does not inhibit the port instructions for P1.7/MDY. Therefore the state of both port line and flip-flop may be read in and the port flip-flop may be written by port instructions. However, the port flip-flop of P1.7/MDY must remain set to avoid conflicts between melody and port outputs. When the HGF contents are zero while EMO = 1, P1.7/MDY is in the logic HIGH state. DESCRIPTION
1997 Apr 16
7
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
PCD3755A; PCD3755E; PCD3755F
handbook, full pagewidth
8
MELODY CONTROL REGISTER square wave
PORT/MELODY OUTPUT LOGIC
P1.7/ MDY
8 HGF REGISTER
DIGITAL SINE WAVE SYNTHESIZER DAC SWITCHED CAPACITOR BANDGAP VOLTAGE REFERENCE DAC SWITCHED CAPACITOR LOW-PASS FILTER
8 INTERNAL BUS
RC LOW-PASS FILTER
MLC416
TONE
8 LGF REGISTER
DIGITAL SINE WAVE SYNTHESIZER
Fig.4 Block diagram of the frequency generator and melody output (P1.7/MDY) section.
1997 Apr 16
8
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
6.2 Melody output (P1.7/MDY)
PCD3755A; PCD3755E; PCD3755F
The melody output (P1.7/MDY) is very useful for generating musical tones when a purely sinusoidal signal is not required, such as for ringer applications. The square wave (duty cycle = 1223 or 52%) will include the attenuated harmonics of the base frequency, which is defined by the contents of the HGF register (Table 3). However, even higher frequency tones may be produced since the low-pass filtering on the TONE output is not applied to the P1.7/MDY output. This results in the minimum decimal value x in the HGF register being 2 for the P1.7/MDY output, rather than 60 for the TONE output - the value shown in equation (1). A sinusoidal TONE output is produced at the same time as the melody square wave, but due to the filtering, the higher frequency sine waves with x < 60 will not appear at the TONE output. Since the melody output is shared with P1.7, the port flip-flop of P1.7 has to be set HIGH before using the melody output. This is to avoid conflicts between melody and port outputs. The melody output drive depends on the configuration of port P1.7/MDY; see Chapter 14, Table 24. 6.3 Frequency registers
The amplitude of the Low group frequency sine wave is attenuated by 2 dB compared to the amplitude of the High group frequency sine wave. The two sine waves are summed and then filtered by an on-chip switched capacitor and RC low-pass filters. These guarantee that all DTMF tones generated fulfil the CEPT recommendations with respect to amplitude, frequency deviation, total harmonic distortion and suppression of unwanted frequency components. The value 00H in a frequency register stops the corresponding digital sine synthesizer. If both frequency registers contain 00H, the whole frequency generator is shut off, resulting in lower power consumption. The frequency of the sine wave generated `f' is dependent on the clock frequency `fxtal' and the decimal value `x' held in the frequency registers (HGF and LGF). The variables are related by the equation: f xtal where 60 x 255 f = -------------------------------(1) [ 23 ( x + 2 ) ] The frequency limitation given by x 60 is due to the low-pass filters which would attenuate higher frequency sine waves.
The two frequency registers HGF and LGF define two frequencies. From these, the digital sine synthesizers together with the Digital-to-Analog Converters (DACs) construct two sine waves. Their amplitudes are precisely scaled according to the bandgap voltage reference. This ensures tone output levels independent of supply voltage and temperature.
1997 Apr 16
9
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
6.4 DTMF frequencies 6.5
PCD3755A; PCD3755E; PCD3755F
Modem frequencies
Assuming an oscillator frequency fxtal = 3.58 MHz, the DTMF standard frequencies can be implemented as shown in Table 6. The relationships between telephone keyboard symbols, DTMF frequency pairs and the frequency register contents are given in Table 7. Table 6 DTMF standard frequencies and their implementation; value = LGF, HGF contents FREQUENCY (Hz) STANDARD 697 770 852 941 1209 1336 1477 1633 GENERATED 697.90 770.46 850.45 943.23 1206.45 1341.66 1482.21 1638.24 DEVIATION (%) 0.13 0.06 -0.18 0.24 -0.21 0.42 0.35 0.32 (Hz) 0.90 0.46 -1.55 2.23 -2.55 5.66 5.21 5.24
Again assuming an oscillator frequency fxtal = 3.58 MHz, the standard modem frequencies can be implemented as in Table 8. It is suggested to define the frequency by the HGF register while the LGF register contains 00H, disabling Low Group Frequency generation. Table 8 HGF VALUE (HEX) 9D 82 8F 79 80 45 76 48 5C 52 4B 44 Notes 1. Standard is V.21. 2. Standard is Bell 103. 3. Standard is Bell 202. 4. Standard is V.23. Standard modem frequencies and their implementation FREQUENCY (Hz) MODEM 980(1) 1180(1) 1070(2) 1270(2) 1200(3) 2200(3) 1300(4) 2100(4) 1650(1) 1850(1) 2025(2) 2225(2) GENERATED 978.82 1179.03 1073.33 1265.30 1197.17 2192.01 1296.94 2103.14 1655.66 1852.77 2021.20 2223.32 DEVIATION (%) -0.12 -0.08 0.31 -0.37 -0.24 -0.36 -0.24 0.15 0.34 0.15 -0.19 -0.08 (Hz) -1.18 -0.97 3.33 -4.70 -2.83 -7.99 -3.06 3.14 5.66 2.77 -3.80 -1.68
VALUE (HEX) DD C8 B5 A3 7F 72 67 5D Table 7
Dialling symbols, corresponding DTMF frequency pairs and frequency register contents LGF VALUE (HEX) A3 DD DD DD C8 C8 C8 B5 B5 B5 DD C8 B5 A3 A3 A3 HGF VALUE (HEX) 72 7F 72 67 7F 72 67 7F 72 67 5D 5D 5D 5D 7F 67
TELEPHONE DTMF FREQ. KEYBOARD PAIRS SYMBOLS (Hz) 0 1 2 3 4 5 6 7 8 9 A B C D * # (941, 1336) (697, 1209) (697, 1336) (697, 1477) (770, 1209) (770, 1336) (770, 1477) (852, 1209) (852, 1336) (852, 1477) (697, 1633) (770, 1633) (852, 1633) (941, 1633) (941, 1209) (941, 1477)
1997 Apr 16
10
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
6.6 Musical scale frequencies 7
PCD3755A; PCD3755E; PCD3755F
EEPROM AND TIMER 2 ORGANIZATION
Finally, two octaves of musical scale in steps of semitones can be realized, again assuming an oscillator frequency fxtal = 3.58 MHz (Table 9). It is suggested to define the frequency by the HGF register while the LGF contains 00H, disabling Low Group Frequency generation. Table 9 Musical scale frequencies and their implementation HGF VALUE (HEX) F8 EA DD D0 C5 B9 AF A5 9C 93 8A 82 7B 74 6D 67 61 5C 56 51 4D 48 44 40 3D FREQUENCY (Hz) STANDARD(1) 622.3 659.3 698.5 740.0 784.0 830.6 880.0 923.3 987.8 1046.5 1108.7 1174.7 1244.5 1318.5 1396.9 1480.0 1568.0 1661.2 1760.0 1864.7 1975.5 2093.0 2217.5 2349.3 2489.0 GENERATED 622.5 659.5 697.9 741.1 782.1 832.3 879.3 931.9 985.0 1044.5 1111.7 1179.0 1245.1 1318.9 1402.1 1482.2 1572.0 1655.7 1768.5 1875.1 1970.0 2103.3 2223.3 2358.1 2470.4
NOTE D#5 E5 F5 F#5 G5 G#5 A5 A#5 B5 C6 C#6 D6 D#6 E6 F6 F#6 G6 G#6 A6 A#6 B6 C7 C#7 D7 D#7 Note
The PCD3755A, PCD3755E and PCD3755F have 128 bytes of Electrically Erasable Programmable Read-Only Memory (EEPROM). Such non-volatile storage provides data retention without the need for battery backup. In telecom applications, the EEPROM is used for storing redial numbers and for short dialling of frequently used numbers. More generally, EEPROM may be used for customizing microcontrollers, such as to include a PIN code or a country code, to define trimming parameters, to select application features from the range stored in ROM. The most significant difference between a RAM and an EEPROM is that a bit in EEPROM, once written to a logic 1, cannot be cleared by a subsequent write operation. Successive write accesses actually perform a logical OR with the previously stored information. Therefore, to clear a bit, the whole byte must be erased and re-written with the particular bit cleared. Thus, an erase-and-write operation is the EEPROM equivalent of a RAM write operation. Whereas read access times to an EEPROM are comparable to RAM access times, write and erase accesses are much slower at 5 ms each. To make these operations more efficient, several provisions are available in the PCD3755A, PCD3755E and PCD3755F. First, the EEPROM array is structured into 32 four-byte pages (see Fig.5) permitting access to 4 bytes in parallel (write page, erase/write page and erase page). It is also possible to erase and write individual bytes. Finally, the EEPROM address register provides auto-incrementing, allowing very efficient read and write accesses to sequential bytes. To simplify the erase and write timing, the derivative 8-bit down-counter (Timer 2) with reload register is provided. In addition to EEPROM timing, Timer 2 can be used for general real-time tasks, such as for measuring signal duration and for defining pulse widths.
1. Standard scale based on A4 @ 440 Hz.
1997 Apr 16
11
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
PCD3755A; PCD3755E; PCD3755F
handbook, full pagewidth
5 8 EEPROM ADDRESS REGISTER
2 2 : 4 DECODER EEPROM LATCH 0 EEPROM LATCH 1 EEPROM LATCH 2 EEPROM LATCH 3 F0 F1 128-byte EEPROM ARRAY (32 4-byte PAGES) F2 F3 5 : 32 DECODER
8
8 8 EEPROM TEST REGISTER
8 EEPROM CONTROL REGISTER
8 TIMER 2 RELOAD REGISTER 8 8 TIMER 2 REGISTER (T2) 8 INTERNAL BUS
1 f 480 xtal
MGB824
T2F set on underflow
Fig.5 Block diagram of the EEPROM and Timer 2.
1997 Apr 16
12
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
7.1 7.1.1 EEPROM registers EEPROM CONTROL REGISTER (EPCR)
PCD3755A; PCD3755E; PCD3755F
The behaviour of the EEPROM and Timer 2 section is defined by the EEPROM Control Register. Table 10 EEPROM Control Register (address 04H, access type R/W) 7 STT2 6 ET2I 5 T2F 4 EWP 3 MC3 2 MC2 1 MC1 0 0
Table 11 Description of EPCR bits BIT 7 6 5 4 3 2 1 0 MNEMONIC STT2 ET2I T2F EWP MC3 MC2 MC1 - This bit is set to a logic 0. DESCRIPTION Start T2. If STT2 = 0, then Timer 2 is stopped; T2 value held. If STT2 = 1, then T2 decrements from reload value. Enable T2 interrupt. If ET2I = 0, then T2F event cannot request interrupt. If ET2I = 1, then T2F event can request interrupt. Timer 2 flag. Set when T2 underflows (or by program); reset by program. Erase or write in progress (EWP). Set by program (EWP starts EEPROM erase and/or write and Timer 2). Reset at the end of EEPROM erase and/or write. Mode control 3 to 1. These three bits in conjunction with bit EWP select the mode as shown in Table 12.
Table 12 Mode selection; X = don't care EWP 0 0 1 1 1 X X X MC3 0 0 0 1 1 0 1 1 MC2 0 1 1 0 1 0 0 1 MC1 0 0 X 0 1 1 1 0 read byte increment mode write page erase/write page erase page not allowed DESCRIPTION
1997 Apr 16
13
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
7.1.2 EEPROM ADDRESS REGISTER (ADDR)
PCD3755A; PCD3755E; PCD3755F
The EEPROM Address Register determines the EEPROM location to which an EEPROM access is directed. As a whole, ADDR auto-increments after read and write cycles to EEPROM, but remains fixed after erase cycles. This behaviour generates the correct ADDR contents for sequential read accesses and for sequential write or erase/write accesses with intermediate page setup. Overflow of the 8-bit counter wraps around to zero. Table 13 EEPROM Address Register (address 01H, access type R/W) 7 0 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 0 AD0
Table 14 Description of ADDR bits BIT 7 6 to 2 1 to 0 MNEMONIC - AD6 to AD2 AD1 to AD0 This bit is set to a logic 0. AD2 to AD6 select one of 32 pages. AD1 and AD0 are irrelevant during erase and write cycles. For read accesses, AD0 and AD1 indicate the byte location within an EEPROM page. During page setup, finally, AD0 and AD1 select EEPROM Latch 0 to 3 whereas AD2 to AD6 are irrelevant. If increment mode (Table 12) is active during page setup, the subcounter consisting of AD0 and AD1 increments after every write to an EEPROM latch, thus enhancing access to sequential EEPROM latches. Incrementing stops when EEPROM Latch 3 is reached, i.e. when AD0 and AD1 are both a logic 1. DESCRIPTION
7.1.3
EEPROM DATA REGISTER (DATR)
Table 15 EEPROM Data Register (address 03H; access type R/W) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
Table 16 Description of DATR bits BIT 7 to 0 MNEMONIC D7 to D0 DESCRIPTION The EEPROM Data Register (DATR) is only a conceptual entity. A read operation from DATR, reads out the EEPROM byte addressed by ADDR. On the other hand, a write operation to DATR, loads data into the EEPROM latch (see Fig.5) defined by bits AD0 and AD1 of ADDR.
7.1.4
EEPROM TEST REGISTER (TST)
The EEPROM Test register is used for testing purposes during device manufacture. It must not be accessed by the device user.
1997 Apr 16
14
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
7.2 EEPROM latches
PCD3755A; PCD3755E; PCD3755F
The four EEPROM latches (EEPROM Latch 0 to 3; Fig.5) cannot be read by user software. Due to their construction, the latches can only be preset, but not cleared. Successive write operations through DATR to the EEPROM latches actually perform a logical OR with the previously stored data in EEPROM. The EEPROM latches are reset at the conclusion of any EEPROM cycle. 7.3 EEPROM flags
page, are irrelevant during write and erase cycles. However, write and erase cycles need not affect all bytes of the page. The EEPROM flags F0 to F3 (see Fig.5) determine which bytes within the EEPROM page are affected by the erase and/or write cycles. A byte whose corresponding EEPROM flag is zero remains unchanged. With erase page, a byte is erased if its corresponding EEPROM flag is set. With write page, data in EEPROM Latch 0 to 3 (Fig.5) are ORed to the individual page bytes if and only if the corresponding EEPROM flags are set. In an erase/write cycle, F0 to F3 select which page bytes are erased and ORed with the corresponding EEPROM latches. ORing, in this event, means that the EEPROM latches are copied to the selected page bytes. The described page-wise organization of erase and write cycles allows up to four bytes to be individually erased or written within 5 ms. This advantage necessitates a preparation step, called page setup, before the actual erase and/or write cycle can be executed. Page setup controls EEPROM latches and EEPROM flags. This will be described in the Sections 7.5.1 to 7.5.5. 7.5.1 PAGE SETUP
The four EEPROM flags (F0 to F3; Fig.5) cannot be directly accessed by user software. An EEPROM flag is set as a side-effect when the corresponding EEPROM latch is written through DATR. The EEPROM flags are reset at the conclusion of any EEPROM cycle. 7.4 EEPROM macros
The instruction sequence used in an EEPROM access should be treated as an indivisible entity. Erroneous programs result if ADDR, DATR, RELR or EPCR are inadvertently changed during an EEPROM cycle or its setup. Special care should be taken if the program may asynchronously divert due to an interrupt. Particularly, a new access to the EEPROM may only be initiated when no write, erase or erase/write cycles are in progress. This can be verified by reading bit EWP (register EPCR). For write, erase and erase/write cycles, it is assumed that the Timer 2 Reload Register (RELR) has been loaded with the appropriate value for a 5 ms delay, which depends on fxtal (see Table 23). The end of a write, erase or erase/write cycle will be signalled by a cleared EWP and by a Timer 2 interrupt provided that ET2I = 1 and that the derivative interrupt is enabled. 7.5 EEPROM access
One read, one write, one erase/write and one erase access are defined by bits EWP and MC1 to MC3 in the EPCR register; see Table 10. Read byte retrieves the EEPROM byte addressed by ADDR when DATR is read. Read cycles are instantaneous. Write and erase cycles take 5 ms, however. Erase/write is a combination of an erase and a subsequent write cycle, consequently taking 10 ms. As their names imply, write page, erase page and erase/write page are applied to a whole EEPROM page. Therefore, bits AD0 and AD1 of register ADDR (see Table 13), defining the byte location within an EEPROM
Page setup is a preparation step required before write page, erase page and erase/write page cycles. As previously described, these page operations include single-byte write, erase and erase/write as a special event. EEPROM flags F0 to F3 determine which page bytes will be affected by the mentioned page operations. EEPROM Latch 0 to 3 must be preset through DATR to specify the write cycle data to EEPROM and to set the EEPROM flags as a side-effect. Obviously, the actual preset value of the EEPROM latches is irrelevant for erase page. Preset of one, two, three or all four EEPROM latches and the corresponding EEPROM flags can be performed by repeatedly defining ADDR and writing to DATR (see Table 17). If more than one EEPROM latch must be preset, the subcounter consisting of AD0 and AD1 can be induced to auto-increment after every write to DATR, thus stepping through all EEPROM latches. For this purpose, increment mode (Table 12) must be selected. Auto-incrementing stops at EEPROM Latch 3. It is not mandatory to start at EEPROM Latch 0 as in shown in Table 18. Note that AD2 to AD6 are irrelevant during page setup. They will usually specify the intended EEPROM page, anticipating the subsequent page cycle.
1997 Apr 16
15
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
From now on, it will be assumed that AD2 to AD6 will contain the intended EEPROM page address after page setup. Table 17 Page setup; preset INSTRUCTION MOV A, #addr MOV ADDR, A MOV A, #data MOV DATR, A RESULT address of EEPROM latch send address to ADDR load write, erase/write or erase data send data to addressed EEPROM latch
PCD3755A; PCD3755E; PCD3755F
To actually copy the data from the EEPROM latches, the corresponding bytes in the page should previously have been erased. The EEPROM latches are preset as described in Section 7.5.1. The actual transfer to the EEPROM is then performed as shown in Table 20. The last instruction also starts Timer 2. The data in the EEPROM latches are ORed with that in the corresponding page bytes within 5 ms. A single-byte write is simply a special case of `write page'. ADDR auto-increments after the write cycle. If AD0 and AD1 addressed EEPROM Latch 3 prior to the write cycle, ADDR will point to the next EEPROM page (by bits AD2 to AD6) and to EEPROM Latch 0 (by bits AD0 and AD1). This allows efficient coding of multi-page write operations. Table 20 Write page INSTRUCTION MOV A, #EWP + MC2 MOV EPCR, A 7.5.4 RESULT `write page' control word start `write page' cycle
Table 18 Page setup; auto-incrementing INSTRUCTION MOV A, #MC2 MOV EPCR, A MOV A, #baddr MOV ADDR, A MOV A, R0 MOV DATR, A MOV A, R1 MOV DATR, A MOV A, R2 MOV DATR, A MOV A, R3 MOV DATR, A 7.5.2 RESULT increment mode control word select increment mode EEPROM Latch 0 address (AD0 = AD1 = 0) send EEPROM Latch 0 address to ADDR load 1st byte from Register 0 send 1st byte to EEPROM Latch 0 load 2nd byte from Register 1 send 2nd byte to EEPROM Latch 1 load 3rd byte from Register 2 send 3rd byte to EEPROM Latch 2 load send 4th 4th byte from Register 3 byte to EEPROM Latch 3
ERASE/WRITE PAGE
The EEPROM latches are preset as described in Section 7.5.1. The page byte corresponding to the asserted flags (among F0 to F3) are erased and re-written with the contents of the respective EEPROM latches. The last instruction also starts Timer 2. Erasure takes 5 ms upon which Timer Register T2 reloads for another 5 ms cycle for writing. The top cycles together take 10 ms. A single-byte erase/write is simply a special event of `erase/write page'. ADDR auto-increments after the write cycle. If AD0 and AD1 addressed EEPROM Latch 3 prior to the write cycle, ADDR will point to the next EEPROM page (by AD2 to AD6) and to EEPROM Latch 0 (by AD0 and AD1). This allows efficient coding of multi-page erase/write operations. Table 21 Erase/write page INSTRUCTION MOV A, #EWP + MC3 MOV EPCR, A RESULT `erase/write page' control word start `erase/write page' cycle
READ BYTE
Since ADDR auto-increments after a read cycle regardless of the page boundary, successive bytes can efficiently be read by repeating the last instruction. Table 19 Read byte INSTRUCTION MOV ADDR, A MOV A, DATR 7.5.3 WRITE PAGE RESULT send address to ADDR read EEPROM data
MOV A, #RDADDR load read address
The write cycle performs a logical OR between the data in the EEPROM latches and that in the addressed EEPROM page. 1997 Apr 16 16
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
7.5.5 ERASE PAGE
PCD3755A; PCD3755E; PCD3755F
The EEPROM flags are set as described in Section 7.5.1. The corresponding page bytes are erased. The last instruction also starts Timer 2. Erasure takes 5 ms. A single-byte erase is simply a special case of `erase page'. Note that ADDR does not auto-increment after an erase cycle. Table 22 Erase page INSTRUCTION RESULT
The second underflow of an erase/write cycle and the first underflow of write page and erase page conclude the corresponding EEPROM cycle. Timer 2 is stopped, T2F is set whereas EWP and MC1 to MC3 are cleared. Table 23 Reload values as a function of fxtal fxtal (MHz) 1 2 3.58 6 10 16 Note 1. The reload value is (5 x 10-3 x 1480 x fxtal) - 1; fxtal in MHz. 7.6.2 TIMER 2 AS A GENERAL PURPOSE TIMER RELOAD VALUE(1) (HEX) 0A 14 25 3E 68 A6
MOV A, #EWP + MC3 + MC2 + MC1 `erase page' control word MOV EPCR, A start `erase page' cycle
7.6
Timer 2
Timer 2 is a 8-bit down-counter decremented at a rate of 1 480 x fxtal. It may be used either for EEPROM timing or as a general purpose timer. Conflicts between the two applications should be carefully avoided. 7.6.1 TIMER 2 FOR EEPROM TIMING
When used for EEPROM timing, Timer 2 serves to generate the 5 ms intervals needed for erasing or writing the EEPROM. At the decrement rate of 1480 x fxtal, the reload value for a 5 ms interval is a function of fxtal. Table 23 summarizes the required reload values for a number of oscillator frequencies. Timer 2 is started by setting bit EWP in the EPCR. The Timer Register T2 is loaded with the reload value from RELR. T2 decrements to zero. For an erase/write cycle, underflow of T2 indicates the end of the erase operation. Therefore, Timer Register T2 is reloaded from RELR for another 5 ms interval during which the flagged EEPROM latches are copied to the corresponding bytes in the page addressed by ADDR.
When used for purposes other than EEPROM timing, Timer 2 is started by setting STT2. The Timer Register T2 (see Table 26) is loaded with the reload value from RELR. T2 decrements to zero. On underflow, T2 is reloaded from RELR, T2F is set and T2 continues to decrement. Timer 2 can be stopped at any time by clearing STT2. The value of T2 is then held and can be read out. After setting STT2 again, Timer 2 decrements from the reload value. Alternatively, it is possible to read T2 `on the fly' i.e. while Timer 2 is operating.
1997 Apr 16
17
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
8 DERIVATIVE INTERRUPTS 11 IDLE MODE
PCD3755A; PCD3755E; PCD3755F
One derivative interrupt event is defined. It is controlled by bits T2F and ET2I in the EPCR (see Tables 10 and 11). The derivative interrupt event occurs when T2F is set. This request is honoured under the following circumstances: * No interrupt routine proceeds * No external interrupt request is pending * The derivative interrupt is enabled * ET2I is set. The derivative interrupt routine must include instructions that will remove the cause of the derivative interrupt by explicitly clearing T2F. If the derivative interrupt is not used, T2F may directly be tested by the program. Obviously, T2F can also be asserted under program control, e.g. to generate a software interrupt. 9 TIMING
In Idle mode, the frequency generator, the EEPROM and the Timer 2 sections remain operative. Therefore, the IDLE instruction may be executed while an erase and/or write access to EEPROM is in progress. 12 STOP MODE Since the oscillator is switched off, the frequency generator, the EEPROM and the Timer 2 sections receive no clock. It is suggested to clear both the HGF and the LGF registers before entering Stop mode. This will cut off the biasing of the internal amplifiers, considerably reducing current requirements. The Stop mode must not be entered while an erase and/or write access to EEPROM is in progress. The STOP instruction may only be executed when EWP in EPCR is zero. The Timer 2 section is frozen during Stop mode. After exit from Stop mode by a HIGH level on CE/T0, Timer 2 proceeds from the held state. 13 INSTRUCTION SET RESTRICTIONS As RAM space is restricted to 128 bytes, care should be taken to avoid accesses to non-existing RAM locations.
Although thePCD3755A, PCD3755E and PCD3755F operate over a clock frequency range from 1 to 16 MHz, fxtal = 3.58 MHz will usually be chosen to take full advantage of the frequency generator section. 10 RESET In addition to the conditions given in the "PCD33xxA Family" data sheet, all derivative registers are cleared in the reset state.
14 OVERVIEW OF PORT AND POWER-ON-RESET CONFIGURATION Table 24 Port and Power-on-reset configuration See note 1 and 2. PORT 0 TYPE 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2S 1R 2S 2 2S 1R 2S 3 2S 1R 2S PCD3755A 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1R 1R(3) 2S PCD3755E 1S 1S 1S 1S 1S 1S 1S 1S 2S 2S 2S 2S 2S 2S 1S 1S(3) 2S PCD3755F Notes 1. Port output drive: 1 = standard I/O; 2 = open-drain I/O, see "PCD33xxA Family" data sheet. 2. Port state after reset: S = Set (HIGH) and R = Reset (LOW). 3. The Melody Output drive type is push-pull. 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1R 1R(3) 2S PORT 1 PORT 2 VPOR 1.3 V 2.0 V 2.0 V
1997 Apr 16
18
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
15 OTP PROGRAMMING The programming of the PCD3755x and PCD3756x OTPs is based on the OM4260 programmer (Ceibo MP-51), available from Philips. The OM4260 works in conjunction with various adapters supporting the different package types available as listed in Table 25. The low-voltage OTP program memory used is of Anti-Fuse-PROM type and can not be erased after programming. Table 25 OTP programming overview DEVICE Ceibo MP-51 PCD3755x/56x PCD3755x/56x PCD3755x/56x Note PHILIPS TYPE NUMBER OM4260 OM5007 OM5030 OM5037(1)
PCD3755A; PCD3755E; PCD3755F
Thus, the complete OTP memory cannot be tested by the factory, but only partially via a special test array. The average expected yield is 97%. Detailed information on the OTP programming is available in the "PCD3755x Application Note", which is available via your Philips Sales office.
CEIBO TYPE NUMBER MP-51 programmer base PCD3755A / 56A adapter DIP PCD3755A / 56A adapter SO -
SUPPORTED PACKAGE DIP28 SO28
PCD3755A / 56A adapter QFP32 LQFP32
1. As the OM5037 is only a socket converter, the OM5007 is also needed to program the PCD3755x/56x in the LQFP32 package.
1997 Apr 16
19
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
16 SUMMARY OF DERIVATIVE REGISTERS Table 26 Register map ADDR. (HEX) 00 01 02 03 04 05 06 07 not used EEPROM Address Register (ADDR) not used EEPROM Data Register (DATR) EEPROM Control Register (EPCR) Timer 2 Reload Register (RELR) Timer 2 Register (T2) Test Register (TST) High Group Frequency Register (HGF) Low Group Frequency Register (LGF) Melody Control Register (MDYCON) D7 STT2 R7 T2.7 D6 ET21 R6 T2.6 D5 TF2 R5 T2.5 D4 EWP R4 T2.4 0 AD6 AD5 AD4 REGISTER 7 6 5 4
PCD3755A; PCD3755E; PCD3755F
3
2
1
0
R/W
AD3
AD2
AD1
AD0
R/W
D3 MC3 R3 T2.3
D2 MC2 R2 T2.2
D1 MC1 R1 T2.1
D0 0 R0 T2.0
R/W R/W R/W R
only for test purposes; not to be accessed by the device user
08 to 10 not used 11 12 13 H7 L7 0 H6 L6 0 H5 L5 0 H4 L4 0 H3 L3 0 H2 L2 0 H1 L1 0 H0 L0 EMO W W R/W
14 to FF not used 17 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take normal precautions appropriate to handling MOS devices (see "Data Handbook IC14, Section: Handling MOS devices"). 18 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II IO Ptot PO ISS Tstg Tj 1997 Apr 16 supply voltage all input voltages DC input current DC output current total power dissipation power dissipation per output ground supply current storage temperature operating junction temperature 20 PARAMETER -0.8 -0.5 -10 -10 - - -50 -65 - MIN. MAX. +7.0 VDD + 0.5 +10 +10 125 30 +50 +150 90 V V mA mA mW mW mA C C UNIT
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
PCD3755A; PCD3755E; PCD3755F
19 DC CHARACTERISTICS VDD = 1.8 to 6 V; VSS = 0 V; Tamb = -25 to +70 C; all voltages with respect to VSS; fxtal = 3.58 MHz; unless otherwise specified. SYMBOL Supply VDD supply voltage operating RAM data retention in Stop mode IDD operating supply current see Figs 7 and 8; note 2 VDD = 3 V; value HGF or LGF 0 - VDD = 3 V VDD = 5 V; fxtal = 10 MHz VDD = 5 V; fxtal = 16 MHz IDD(idle) supply current (Idle mode) see Figs 9 and 10; note 2 VDD = 3 V; value HGF or LGF 0 - VDD = 3 V VDD = 5 V; fxtal = 10 MHz VDD = 5 V; fxtal = 16 MHz IDD(stp) supply current (Stop mode) see Fig.11; note 3 VDD = 1.8 V; Tamb = 25 C VDD = 1.8 V; Tamb = 70 C Inputs VIL VIH ILI IOL IOH IOH1 LOW level input voltage HIGH level input voltage input leakage current VSS VI VDD VDD = 3 V; VO = 0.4 V; see Fig.12 0 -1 - - 0.3VDD V VDD +1 - - -300 - V A 0.7VDD - - - 1.0 - 5.5 10 A A - - - 0.7 0.25 1.1 1.7 1.4 0.5 3.4 5.0 mA mA mA mA - - - 0.8 0.35 1.5 2.4 1.6 0.7 4.0 6.0 mA mA mA mA see Fig.6 note 1 1.8 1.0 - - 6 6 V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Port outputs LOW level port sink current 0.7 -10 - -0.7 3.5 -30 -140 -3.5 mA A A mA HIGH level pull-up output source VDD = 3 V; VO = 2.7 V; see Fig.13 current VDD = 3 V; VO = 0 V; see Fig.13 HIGH level push-pull output source current VDD = 3 V; VO = 2.6 V; see Fig.14
Tone output (see Fig.15; note 4) VHG(RMS) VLG(RMS) f f VDC Zo Gv THD HGF voltage (RMS) LGF voltage (RMS) frequency deviation DC voltage level output impedance pre-emphasis of group total harmonic distortion Tamb = 25 C; note 5 158 125 -0.6 - - 1.5 - 181 142 - 100 2.0 25 205 160 +0.6 500 2.5 - mV mV % V dB dB
0.5VDD -
1997 Apr 16
21
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
SYMBOL PARAMETER CONDITIONS
PCD3755A; PCD3755E; PCD3755F
MIN. - - TYP. MAX. - - years UNIT
EEPROM (notes 1 and 6) CYt/w tret VPOR endurance (erase/write cycles) data retention time note 7 105 10
Power-on-reset (see Fig.16) Power-on-reset level PCD3755A PCD3755E PCD3755F Oscillator (see Fig.17) gm RF Notes 1. TONE output, EEPROM erase and write require VDD 2.5 V. 2. VIL = VSS; VIH = VDD; open-drain outputs connected to VSS; all other outputs open; value HGF = LGF = 0, unless otherwise specified. a) Maximum values: external clock at XTAL1 and XTAL2 open-circuit. b) Typical values: Tamb = 25 C; crystal connected between XTAL1 and XTAL2. 3. VIL = VSS; VIH = VDD; RESET, T1 and CE/T0 at VSS; crystal connected between XTAL1 and XTAL2; pins T1 and CE/T0 at VSS. 4. Values are specified for DTMF frequencies only (CEPT). 5. Related to the Low Group Frequency (LGF) component (CEPT). 6. After final testing the value of each EEPROM bit is a logic 1, but this cannot be guaranteed after board assembly. 7. Verified on sampling basis. transconductance feedback resistor VDD = 5 V 0.2 0.3 0.4 1.0 1.0 3.0 mS M 0.8 1.5 1.5 1.3 2.0 2.0 1.8 2.5 2.5 V V V
1997 Apr 16
22
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
PCD3755A; PCD3755E; PCD3755F
handbook, halfpage f
18
MLA493
xtal (MHz) 15
handbook, halfpage
6
MGB827
IDD (mA) 16 MHz
12
4
9 guaranteed operating range
2
3.58 MHz HGF or LGF 0 10 MHz
6
3
0
3.58 MHz
0
1
3
5
1
3
5
VDD (V)
7
VDD (V)
7
Measured with crystal between XTAL1 and XTAL2.
Fig.6
Maximum clock frequency (fxtal) as a function of supply voltage (VDD).
Fig.7
Typical operating supply current (IDD) as a function of supply voltage (VDD).
handbook, halfpage
6
MGB828
handbook, halfpage
6
MGB829
IDD (mA) 4 5V
IDD(idle) (mA)
4 16 MHz 3.58 MHz HGF or LGF 0
2
2 10 MHz 3V 3.58 MHz
2
0 1 10 fxtal (MHz) 10
0 1 3 5 VDD (V) 7
Measured with function generator on XTAL1.
Measured with crystal between XTAL1 and XTAL2.
Fig.8
Typical operating supply current (IDD) as a function of clock frequency (fxtal).
Fig.9
Typical supply current in Idle mode (IDD(idle)) as a function of supply voltage (VDD).
1997 Apr 16
23
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
PCD3755A; PCD3755E; PCD3755F
handbook, halfpage
6
MGB830
MGB826
handbook, halfpage
6
IDD(idle) (mA) 4
IDD(stp) (A) 5
4
3
2
5V
2
1
3V 0 1 10 fxtal (MHz) 10
2
0 1 3 5 VDD (V) 7
Measured with function generator on XTAL1.
Fig.10 Typical supply current in Idle mode (IDD(idle)) as a function of clock frequency (fxtal).
Fig.11 Typical supply current in Stop mode (IDD(stp)) as a function of supply voltage (VDD).
MGB831
handbook, halfpage
12
handbook, halfpage
-300
MGB832
IOL (mA) 8
IOH (A) -200
VO = 0 V
4
-100 VO = 0.9VDD
0 1 3 5 VDD (V) 7
0 1 3 5 VDD (V) 7
VO = 0.4 V.
Fig.12 Typical LOW level output sink current (IOL) as a function of supply voltage (VDD).
Fig.13 Typical HIGH level pull-up output source current (IOH) as a function of supply voltage (VDD).
1997 Apr 16
24
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
PCD3755A; PCD3755E; PCD3755F
handbook, halfpage
-12
MGB833
IOH1 (mA) -8
handbook, halfpage VDD
DEVICE TYPE NUMBER (1)
-4
TONE
1 F
50 pF
10 k
VSS
MGB835
0 1 3 5 VDD (V) 7
VO = VDD - 0.4 V.
Fig.14 Typical HIGH level push-pull output source current (IOH1) as a function of supply voltage (VDD).
(1) Device type number: PCD3755A, PCD3755E or PCD3755F.
Fig.15 TONE output test circuit.
MGD495
handbook, halfpage
6
handbook, halfpage
10
MGB834
VDD (V)
gm (mS)
4
1
VPOR = 2.0 V 2 VPOR = 1.3 V
0 -25
10
1
25
75 125 Tamb (C) 70
1
3
5
VDD (V)
7
Fig.16 Typical Power-on-reset level (VPOR) as function of ambient temperature (Tamb).
Fig.17 Typical transconductance (gm) as a function of supply voltage (VDD).
1997 Apr 16
25
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
PCD3755A; PCD3755E; PCD3755F
20 AC CHARACTERISTICS VDD = 1.8 to 6 V; VSS = 0 V; Tamb = -25 to +70 C; all voltages with respect to VSS; unless otherwise specified. SYMBOL tr tf fxtal PARAMETER rise time all outputs fall time all outputs clock frequency see Fig.6 CONDITIONS VDD = 5 V; Tamb = 25 C; CL = 50 pF MIN. - - 1 TYP. 30 30 - MAX. - - 16 UNIT ns ns MHz
1997 Apr 16
26
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
21 PACKAGE OUTLINES
handbook, plastic dual in-line package; 28 leads (600 mil) DIP28: full pagewidth
PCD3755A; PCD3755E; PCD3755F
SOT117-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 28 15 MH wM (e 1)
pin 1 index E
1
14
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 5.1 0.20 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.7 1.3 0.066 0.051 b1 0.53 0.38 0.020 0.014 c 0.32 0.23 0.013 0.009 D (1) 36.0 35.0 1.41 1.34 E (1) 14.1 13.7 0.56 0.54 e 2.54 0.10 e1 15.24 0.60 L 3.9 3.4 0.15 0.13 ME 15.80 15.24 0.62 0.60 MH 17.15 15.90 0.68 0.63 w 0.25 0.01 Z (1) max. 1.7 0.067
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT117-1 REFERENCES IEC 051G05 JEDEC MO-015AH EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
1997 Apr 16
27
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
PCD3755A; PCD3755E; PCD3755F
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 A1 pin 1 index Lp L 1 e bp 14 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 18.1 17.7 0.71 0.69 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT136-1 REFERENCES IEC 075E06 JEDEC MS-013AE EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
1997 Apr 16
28
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
PCD3755A; PCD3755E; PCD3755F
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
SOT358-1
c
y X
24 25
17 16 ZE
A
e E HE wM bp pin 1 index 32 1 e bp D HD wM B vM B 8 ZD vM A 9 detail X L Lp A A2 A 1 (A 3)
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.4 0.3 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.8 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.25 y 0.1 Z D (1) Z E (1) 0.9 0.5 0.9 0.5 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT358 -1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-12-19 97-08-04
1997 Apr 16
29
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM
22 SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 22.1 Reflow soldering
PCD3755A; PCD3755E; PCD3755F
* The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. 22.2.3 METHOD (LQFP AND SO)
Reflow soldering techniques are suitable for all LQFP and SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 22.2 22.2.1 Wave soldering LQFP
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 22.3 22.3.1 DIP SOLDERING BY DIPPING OR BY WAVE
Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP32 (SOT401-1), LQFP48 (SOT313-2), LQFP64 (SOT314-2 and SOT414-1), LQFP80 (SOT315-1) or LQFP100 (SOT407-1). 22.2.2 SO
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 22.4 Repairing soldered joints
Fix LQFP and SO by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. For DIP, apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. 1997 Apr 16 30
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes
23 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCD3755A; PCD3755E; PCD3755F
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 24 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Apr 16
31
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417027/1200/04/pp32
Date of release: 1997 Apr 16
Document order number:
9397 750 02065

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